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Video's Title
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Company
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Views |
| Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology | Cadence |
740 |
| ViVA-XL - Analog Fast Waveform Viewing | Cadence |
3387 |
| Utilizing Relational Database Support in Cadence OrCAD Capture CIS | EMA Design Automation |
990 |
| Using the Pin Editor in Cadence SoC-Encounter | Cadence |
4841 |
| Using Global Timing Debug on a Single Path in Cadence SoC-Encounter | Cadence |
3882 |
| Using --Apply All-- in Cadence SoC-Encounter | Cadence |
1912 |
| TimingDesigner Sigrity Integration for DDR3 | Cadence |
647 |
| Steven Lewis, Product Management Director | Cadence |
2725 |
| Steve Lewis, Product Management Director | Cadence |
1980 |
| Steve Brown, Director of Marketing | Cadence |
803 |
| SimVision Signal Comparison using SimCompare | Cadence |
3037 |
| SimVision Automatic Driver Trace | Cadence |
2013 |
| SimVision Assertion Debug Introduction | Cadence |
2557 |
| Sigrity X: Redefining SI/PI Analysis | Cadence |
3211 |
| Signing off 1B+ Cells Design with Tempus Timing Solution | Cadence |
1959 |
| Sam Chitwood, Sr. Principal Product Engineer | Cadence |
1156 |
| Running Cadence SoC-Encounter...on an iPhone | Cadence |
3921 |
| Quickly Create and Manage e Functional Coverage with Enterprise Planner | Cadence |
1595 |
| Paul Cunningham, VP R&D, Digital and Signoff Group | Cadence |
866 |
| Paul Cunningham, Senior vice president, System and Verification Group | Cadence |
3129 |
| Paul Cunningham, Corporate VP and GM | Cadence |
4441 |
| Partitioning a Design in Cadence SoC-Encounter | Cadence |
5829 |
| Opening of Cadence Building #10, Feb. 2008 | Cadence |
2233 |
| New Spectre Turbo | Cadence |
2565 |
New 12Gb/s SAS and NVM Express IP for Cloud Infrastructure",
Susan Peterson | Cadence |
1405 |
| Moshik Rubin, Product Management Group Director | Cadence |
2684 |
| Mladen Nizic | Cadence |
1412 |
| Mike Vachon, Group Director | Cadence |
1279 |
| Mike Vachon, Group Director | Cadence |
846 |
| Melika Roshandell & Sherry Hess | Cadence |
2184 |
| Machine Learning-Based Cerebrus for Intelligent Chip Design | Cadence |
3152 |
| Low Power Implementation Course Overview | Cadence |
2112 |
| Ken Willis, Director of Product Engineering | Cadence |
2438 |
| K.T. Moore, Group Director | Cadence |
2807 |
| Joules RTL Design Studio Boosts Productivity, QoR | Cadence |
1977 |
| John Pierce, Director of Product Marketing | Cadence |
980 |
| John Cornish, ARM on Cadence's Mixed-Signal Solution and how it helps to design complex SoCs | ARM |
1887 |
| John Chawner, Senior Group Director | Cadence |
2366 |
| John Brennan | Cadence |
641 |
| Joe Hupcey III, Director of Product Management | Cadence |
1585 |
| Introducing Virtuoso Accelerated Parallel Simulator | Cadence |
2368 |
| Interactive Floorplanning in Cadence SoC-Encounter | Cadence |
4458 |
| IC Design with the Cadence Cloud | Cadence |
1600 |
| Hubert Cross, COO | CircuitDevs |
1861 |
| Hitendra Divecha & Brandon Bautz | Cadence |
3335 |
| Hany Elhak, Circuit Simulation with Cadence Spectre X Simulator | Cadence |
1670 |
| Frank Schirrmeister, Sr. Group Director, Solution Marketing | Cadence Design Systems |
1839 |
| Frank Schirrmeister, Sr. Group Director, Product Management | Cadence |
848 |
| Frank Schirrmeister, Sr Group Director Prod Management | Cadence |
647 |
| Frank Schirrmeister, Senior Group Director, Solution Marketing | Cadence |
3711 |
| Frank Schirrmeister | Cadence |
1692 |
| FPGA-Based Prototyping for the Data Center with Cadence Protium X1 | Cadence |
1616 |
| Enterprise Verification Solution | Cadence |
1661 |
| Encounter 8.1 Foundation Flow | Cadence |
4701 |
| Electronics “Least Hurt” Industry in Recession | Cadence Industry Insights |
2452 |
| Detecting System-Level Corner Cases During Low-Power SoC Verification | Cadence |
456 |
| Design Variant Management using Cadence OrCAD Capture CIS | EMA Design Automation |
2173 |
| DAC 1991 Video Parody of the Movie "Amadeus" | Cadence |
8067 |
| CDNLive! Benefits | Cadence |
677 |
| CDNLive EMEA 2013 Keynote: Rudi de Winter, X-FAB, Part 2 of 2 | X-Fab |
910 |
| CDNLive EMEA 2013 Keynote: Rudi de Winter, X-FAB, Part 1 of 2 | X-Fab |
1007 |
| Cadence Software Driven Verification | Cadence |
775 |
| Cadence OnCloud SaaS and e-commerce platform | Cadence |
2683 |
| Cadence new Verisium AI-Driven Verification Platform | Cadence |
2052 |
| Cadence Joint Enterprise Data and AI (JedAI) Platform | Cadence |
1947 |
| Cadence Integrity 3D-IC Platform | Cadence |
3234 |
| Cadence Expands VIP Portfolio | Cadence |
1987 |
| Cadence Certus Closure Solution | Cadence |
1840 |
| Cadence Booth | Cadence |
1908 |
| Cadence announces Allegro Sigrity Power Integrity | Cadence |
1585 |
| Brad Griffin, Product Marketing Director | Cadence |
2591 |
| Brad Griffin | Cadence |
845 |
| Brad Brim, Sr. Staff Product Engineer | Cadence |
1059 |
| AXIEM EM Simulator Within Cadence Virtuoso | AWR |
519 |
| Applying the Latest Technologies to MMIC Design | Agilent EESof |
708 |
| Alberto Sangiovanni-Vincentelli Receives Award | Cadence |
2127 |
| AI-Driven MDAO with Cadence Optimality Explorer | Cadence |
2758 |
"UVM and Silicon Realization",
Tom Anderson | Cadence |
2478 |
"Update: New Memory IP, MIPI & Storage Verification IP, 4 Tutorials, 8 Tech. Papers",
Joe Hupcey III | Cadence |
1527 |
"TSMC Partnership, System Development Suite and 20nm",
John Bruggeman | Cadence |
1490 |
"Studio Suite Cadence Integration",
Martin Timm | CST |
2101 |
"Rapid Prototyping Platform with Easy ASIC Flow",
Juergen Jaeger | Cadence |
2271 |
| "Panel Summary: Is Analog Making a Comeback?", Mladen Nizic | Cadence |
1797 |
| "Palladium System Verification", Michael Young | Cadence |
2475 |
| "OSCI Day", Steve Svoboda | Cadence |
1040 |
"OpenText Remote Connectivity to Cadence Virtuoso",
Stephen Lewis | Open Text |
4845 |
"New Virtuoso APS",
Nebabie Kebebew | Cadence |
2325 |
"New Unified Digital Flow for 28nm Giga-gate/GHz Design",
Rahul Deokar | Cadence |
3471 |
"New PDN Analysis",
Brad Griffin | Cadence |
2959 |
"New Open and Expanded Verification IP Catalog",
Susan Peterson | Cadence |
804 |
"New Encounter Digital Implementation System",
Rahul Deokar | Cadence |
1528 |
"New Easier Allegro Release",
Brad Griffin | Cadence |
1758 |
"New DFM Services for Yield for 40nm and 28nm",
Manoj Chacko | Cadence |
1649 |
"New 3D-IC Design Offering",
Rahul Deokar | Cadence |
3758 |
"My 40nm Design Closure Experience with Cadence Conformal ECO",
Sid Allman, H/W Design Mgr. | Cisco Systems |
3065 |
"Conformal ECO Designer Automates Frontend Changes",
Kenneth Chang | Cadence |
2024 |
"Cadence Online Community",
David Stokes | Cadence |
1158 |
"Allegro Update: PDN Analysis, Multi-Gigabit AMI Models, DDR Memory Kits",
Brad Griffin | Cadence |
2922 |
"28nm Design Creation",
Wei Lii Tan | Cadence |
1947 |
| AXIEM EM Simulator Within Cadence Virtuoso | AWR |
321 |
