Video's Title
AXIEM EM Simulator Within Cadence VirtuosoAWR 154
"28nm Design Creation",
Wei Lii Tan
Cadence 1729
"Allegro Update: PDN Analysis, Multi-Gigabit AMI Models, DDR Memory Kits",
Brad Griffin
Cadence 2661
"Cadence Online Community",
David Stokes
Cadence 1088
"Conformal ECO Designer Automates Frontend Changes",
Kenneth Chang
Cadence 1783
"My 40nm Design Closure Experience with Cadence Conformal ECO",
Sid Allman, H/W Design Mgr.
Cisco Systems 2881
"New 3D-IC Design Offering",
Rahul Deokar
Cadence 3467
"New DFM Services for Yield for 40nm and 28nm",
Manoj Chacko
Cadence 1433
"New Easier Allegro Release",
Brad Griffin
Cadence 1510
"New Encounter Digital Implementation System",
Rahul Deokar
Cadence 1283
"New Open and Expanded Verification IP Catalog",
Susan Peterson
Cadence 801
"New PDN Analysis",
Brad Griffin
Cadence 2808
"New Unified Digital Flow for 28nm Giga-gate/GHz Design",
Rahul Deokar
Cadence 3330
"New Virtuoso APS",
Nebabie Kebebew
Cadence 2039
"OpenText Remote Connectivity to Cadence Virtuoso",
Stephen Lewis
Open Text 4804
"OSCI Day", Steve SvobodaCadence 1020
"Palladium System Verification", Michael YoungCadence 2380
"Panel Summary: Is Analog Making a Comeback?", Mladen NizicCadence 1658
"Rapid Prototyping Platform with Easy ASIC Flow",
Juergen Jaeger
Cadence 2053
"Studio Suite Cadence Integration",
Martin Timm
CST 1858
"TSMC Partnership, System Development Suite and 20nm",
John Bruggeman
Cadence 1278
"Update: New Memory IP, MIPI & Storage Verification IP, 4 Tutorials, 8 Tech. Papers",
Joe Hupcey III
Cadence 1392
"UVM and Silicon Realization",
Tom Anderson
Cadence 2239
Alberto Sangiovanni-Vincentelli Receives AwardCadence 1979
Applying the Latest Technologies to MMIC DesignAgilent EESof 587
AXIEM EM Simulator Within Cadence VirtuosoAWR 234
Brad Brim, Sr. Staff Product EngineerCadence 928
Brad GriffinCadence 726
Brad Griffin, Product Marketing DirectorCadence 2415
Cadence announces Allegro Sigrity Power IntegrityCadence 1444
Cadence BoothCadence 1737
Cadence Expands VIP PortfolioCadence 1872
Cadence Software Driven VerificationCadence 622
Cadence to Acquire AWR from National InstrumentsCadence 2025
CDNLive EMEA 2013 Keynote: Rudi de Winter, X-FAB, Part 1 of 2X-Fab 866
CDNLive EMEA 2013 Keynote: Rudi de Winter, X-FAB, Part 2 of 2X-Fab 785
CDNLive! BenefitsCadence 675
DAC 1991 Video Parody of the Movie "Amadeus"Cadence 7922
Design Variant Management using Cadence OrCAD Capture CISEMA Design Automation 2026
Detecting System-Level Corner Cases During Low-Power SoC VerificationCadence 339
Electronics “Least Hurt” Industry in RecessionCadence Industry Insights 2399
Encounter 8.1 Foundation FlowCadence 4332
Enterprise Verification SolutionCadence 1557
FPGA-Based Prototyping for the Data Center with Cadence Protium X1Cadence 1395
Frank SchirrmeisterCadence 1569
Frank Schirrmeister, Senior Group Director, Solution MarketingCadence 1994
Frank Schirrmeister, Senior Group Director, Solution MarketingCadence 1926
Frank Schirrmeister, Sr Group Director Prod ManagementCadence 537
Frank Schirrmeister, Sr. Group Director, Product ManagementCadence 713
Hany Elhak, Circuit Simulation with Cadence Spectre X SimulatorCadence 1409
Hitendra Divecha & Brandon BautzCadence 1754
Hubert Cross, COOCircuitDevs 1618
IC Design with the Cadence CloudCadence 1313
Interactive Floorplanning in Cadence SoC-EncounterCadence 4249
Introducing Virtuoso Accelerated Parallel SimulatorCadence 2236
Joe Hupcey III, Director of Product ManagementCadence 1489
John BrennanCadence 520
John Cornish, ARM on Cadence's Mixed-Signal Solution and how it helps to design complex SoCsARM 1693
John Pierce, Director of Product MarketingCadence 863
K.T. Moore, Group DirectorCadence 2589
Ken Willis, Director of Product EngineeringCadence 2097
Low Power Implementation Course OverviewCadence 1972
Mike Vachon, Group DirectorCadence 737
Mike Vachon, Group DirectorCadence 1154
Mladen NizicCadence 1272
Moshik Rubin, Product Management Group DirectorCadence 2273
New 12Gb/s SAS and NVM Express IP for Cloud Infrastructure",
Susan Peterson
Cadence 1225
New Spectre TurboCadence 2431
Opening of Cadence Building #10, Feb. 2008Cadence 2078
Partitioning a Design in Cadence SoC-EncounterCadence 4990
Paul Cunningham, Corporate VP and GMCadence 2668
Paul Cunningham, VP R&D, Digital and Signoff GroupCadence 715
Quickly Create and Manage e Functional Coverage with Enterprise PlannerCadence 1476
Running Cadence SoC-Encounter...on an iPhoneCadence 3781
Sam Chitwood, Sr. Principal Product EngineerCadence 968
Sharon Rosenberg, Sr Solution ArchitectCadence 2262
SimVision Assertion Debug IntroductionCadence 2143
SimVision Automatic Driver TraceCadence 1709
SimVision Signal Comparison using SimCompareCadence 2169
Steve Brown, Director of MarketingCadence 663
Steven Lewis, Product Management DirectorCadence 1197
TimingDesigner Sigrity Integration for DDR3Cadence 498
Using --Apply All-- in Cadence SoC-EncounterCadence 1752
Using Global Timing Debug on a Single Path in Cadence SoC-EncounterCadence 3606
Using the Pin Editor in Cadence SoC-EncounterCadence 4226
Utilizing Relational Database Support in Cadence OrCAD Capture CISEMA Design Automation 901
ViVA-XL - Analog Fast Waveform ViewingCadence 3033
Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory TechnologyCadence 583
Total 88 links listed, not including links in sub-categories.

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