Hi Gabe,
In the days since I started working at 1.5um things have certainly progressed! Despite all these advances in increasing physical awareness during synthesis one important aspect hasn’t changed though – a poorly constrained design makes it almost impossible to efficiently close timing. At Atrenta we’ve seen numerous rudimentary problems encountered by our customers (clocks not reaching vast swathes of registers for example) which would unfortunately not have been addressed by physical awareness. We continue to see demand for our SpyGlass-Constraints validation and management solutions from leading edge users who simply can’t deal with the iterations they face in closing their constraints. And when you talk about timing exceptions things can start to get even more scary.
If you really want to take a more abstract view of the problem, I’d suggest that we as an industry need to deal with the ‘garbage in, garbage out’ problem. The 2X runtime improvement you quote is certainly of value to users, but a bigger problem is the 15-20 iterations they need to go through before they have a set of timing constraints which they trust and which actually constrain their design completely. RTL Signoff is more than having good quality RTL, it’s about having all the ancillary data (timing constraints included) to actually make effective use of that RTL. Given the choice of chipping away at the problem in the backend or creating a much better starting point, I know which I’d go for.
Cheers,
Ron Craig
Atrenta Inc.
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Increasing The Level Of Abstraction Of IC Design
Garbage in , Garbage out? 
