Dear all,

I am working on "Prediction of Glitches and Hazards at transistor level". I have to analyse glitches and develop metrics to predict them. The anaylsis will be done at transistor level and i have to implement a mechanism to record the incomplete transitions during simulation. To do this I am using various tools of Cadence.

I am generating the netlist (3 bit Adder for example) using synopsys design analyzer. I then create a schematic using Cadence Virtuoso and supply it with input streams. Later I analyse the outputs. This is what I am suppossed to do.

The problem :

1) How can I convert the inputs which are in binary digital format to analog voltages so that i can give them to my schematic as inputs. I have heard about this "BitGen" program which does this but never tried it. Any other Cadence alternatives you can suggest ?

2) How can I record the incomplete transitions during simulation at transistor level.

3) I have to estimate the Glitches and other parameters (like the No.of Glitches etc..). To do this i have to analyse the wave forms and i cannot do this manually. Can any one suggest any good alternative that i can use in this kind of a scenario. I have heard of "OCEAN" scripting language, SKILL, TCL etc.. can they be useful to analyse the wave forms.

4) Can i automate the whole above processes, instead of doing it manually. Like starting cadence tools (SpectreS simulator), giving inputs, and analysing outputs. If so how can i do that ?

A very lengthy post i believe. Please take some time for this newbie and help me out.

Thanks in advance,

kamesh.

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