Sunnyvale CA ( Fulltime with End Client )

 Qualifications
Hands-on experience in physical design of large SoC’s
Extensive experience in clock and power implementation methodologies and practices in low power designs
Deep understanding of hierarchical/timing driven layout methodologies and practices
Experience with integrating various type of hardened IP modules
Ability to collaborate with RTL, synthesis, STA engineers in timing closure, gate level verification and debug
Familiarity with various ECO flows and techniques
Good communication skills
5+ years physical design experience with 3+ Year experience in Synopsys and/or Magma physical design tool suites
BSEE required, MSEE preferred