This press release reads as a new product announcement, but in effect Cadence VPCD is a
a respin of VPCM, a product based on technology they acquired from Celestry that has been
shipping bundled in MMSIM (simulators package) for some time now. As a matter of fact,
I recognize one of the customer quotes from here:
Other products compete for the same slot, such as Lorentz Solutions' Peakview and Helic's
VeloceRF, both of which introduced support for 90- and 65-nm process nodes long ago.
Lorentz offers a versatile API for developing custom spiral inductor PCells, while Helic's
is the only solution that provides mutual inductance extraction (spiral to spiral, also supporting
interconnect RLCK) without resorting to time-consuming EM analysis.
Both tools boast customer wins with Tier 1 IDM and fabless companies.
Cadence have reportedly spent considerable effort in bringing VPCM (now VPCD) to shape, but they
need to get the use model right. Foundries and designers still have to spend significant time and
resources to construct a PCell library which is 100% DRC and DFM-clean in 90/65nm CMOS. Also,
accurately simulating single inductors and transformers is only part of the problem; extraction
of complex layouts with multiple inductors and interconnects becomes necessary. For instance, how
about VPCD-AssuraRF linkages?