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04/04/06 09:32 AM
Optimal Verification new Report this article as Inappropriate to us !!!Login to Reply

Optimal Verification

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Dave Doman
04/04/06 09:32 AM
Appropriate Verification new Report this article as Inappropriate to us !!!Login to Reply

This I will agree with fully. Failure of a design, either partially or fully, is a design issue (and that includes verification). During a design process, an engineer needs to think through "how will this aspect of this design fail" and needs to address the appropriate level of verification (including what tool and what view of what model of reality is needed to be tested and to what level). Just "pressing the button" is bad. ALSO, however, "pushing verificaion to the n'th degree is just as bad. Now, although inadequate verification usually leads to not uncovering the issue that causes the spectacular failure, I believe that this is a fault of not thinking through the problem as opposed to not testing enough.

04/04/06 09:56 AM
Design for Verification new Report this article as Inappropriate to us !!!Login to Reply

Design For Verification holds the key here. Nothing would be far more important than leveraging the designers intention to value add on verification efforts. There are lots of technology and tools to help in that area which add value to this effort. Mainly focusing on assertions, multilevel design. Also formal techniques which are suitable for white-box testing eliminate simple functional bugs at block level. An interesting paper by Synopsys on this topic. http://www.synopsys.com/products/simulation/dfv_wp.html

04/05/06 09:36 AM
Gerry new Report this article as Inappropriate to us !!!Login to Reply

I was hoping for a clear definition of the term "Verification" At www.ictooling.com I focus on Physical Verification, this article is not quite right. It is essential that the Physical Veritfication (DRC) be 100% correct(DRC, LVS, device extraction) When digital verification (simulation) requires that test vectors be suppled to stimulate the device, then the concept of 100% verification becomes difficult as the input vector space becomes large. In analog verification (simulation) the issues of process variation adds another variation that makes 100% coverage difficult. In Physical Verification, the DRC deck is assigned a gold standard and 100% coverage is usually required (exceptions for Memorys and special cases do exist) This area is also getting to be problematic as DFM and YIELD requirements have added "recommended rules" that do not always require 100 coverage.

Dave Doman
04/06/06 12:25 PM
Does 100% compliance o DRC mean what people think it means? new Report this article as Inappropriate to us !!!Login to Reply

Let's be careful. DRC being "gold standard" and needing "100% compliance" is problematic at many tech nodes (as the previous reviewer pointed out for memories, etc). but for stdcells and APR area as well. Any time a fab "signs off" on a DRC failure, then by default, the deck is NOT golden. In the long run, the fab may choose to keep the offending rule and have the design house jump through the hoop, but if a process can accept a "signed off" issue once and yield product, then it COULD do so at any other time (for that rule). On the other hand, as the previous reviewer pointed out, DRC alone isn't enough anymore,... DFM and the "well how lucky do you feal" syndrome is raising it's dirty (harry) head.

(Stranger )
03/26/20 09:54 AM
Re: Optimal Verification Report this article as Inappropriate to us !!!Login to Reply

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(Stranger )
04/10/20 07:20 AM
Re: Optimal Verification new Report this article as Inappropriate to us !!!Login to Reply

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