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(Stranger )
01/06/11 04:44 AM
VHDL Linting Tool Report this article as Inappropriate to us !!!Login to Reply


Does anyone have experience of any linting type tools for VHDL. 

I'm looking for something that can be used to uphold coding standards or highlight potential synthesis issues at an early stage.






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Verific: SystemVerilog & VHDL Parsers

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