(Unregistered) 04/21/08 05:25 PM
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IP Standards: No room for Mr. Nice Guy
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IP Standards: No room for Mr. Nice Guy Use this link to read the full article
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Ron (Unregistered) 04/21/08 05:25 PM
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This discussion shows the progress as wel as the holes in the approaches being taken to develop IP standards. That is good -since we need to see the holes to try to fix them. We will only have industry colaboration when many in a particular industry see a dollar advantage. See Victor's comment about Cadence and their decision to open up Verilog. Without that decision, the rest of the industry would have bypassed them with further intensive development of the defacto HDL at that time - VHDL. With Cadence's decision to open up Verilog, they had a chance to jump ahead and be a leader. There is another view of the standards technology development. That view deals with "interoperability." Interoperability development can be looked at as a "standards development motivator." There is a world-wide organization called IFIP - International Federation for Information processing. While international in its membership, it is mainly known well in Europe. They do not develop standards, but their technical activities are oriented towards design and business interaction methods. IFIP TC10 deals largely with Computer Systems Technology. IFIP TC5 deals largely with Information Technology Applications. Enterprise Interoperability, Enterprise Integration, Infrastructure for Virtual Enterprises, the Product Realization Process, are just some of the technical activities of TC5. My point here is that taking an orthoganl view of IP, the standards work mentioned in the article could be viewed as orthoganal to the technical methodologies being investigated by IFP Technical Committees. Such an orthoganal approach might help advance the IP work underway in the US.
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engineerfinder (Stranger
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04/22/08 02:50 PM
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Re: Only Part of the Picture
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<p>I think that Cadence really does not have strong competition in regard to design tools as nearly every semiconductor company uses Cadence. In fact, even smaller companies that cannot afford the entire cadence toolset still use a portion. </p><p>I have several Digital/Analog Design Engineering positions open here in California for a new CMOS Image Sensor group for one of the TOP semiconductor companies in the world. Cadence is required.</p><p>If anyone is interested in joining the tam, this company will pay 100% relocation.</p><p> Send resumes to:</p><p>engineerfinder@gmail.com</p><p> </p>
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MarryCole (Stranger
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09/23/20 02:11 AM
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<p>ould have bypassed them with further intensive development of the defacto HDL at that time - VHDL.</p>
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