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(Stranger )
07/16/10 02:12 PM
Re: DAC 2010 Report from the Floor Report this article as Inappropriate to us !!!Login to Reply

Boolean equivalence checking is part of the digital design verification process, and may be done at multiple points in the design flow. Implementation tools make many changes to the netlist (clock tree insertion, timing optimizations such as cloning and buffering, etc., some of which are still manual) and require a separate check to insure functionality is not broken.

It is not simply QA for tool writers.

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*DAC 2010 Report from the Floor  07/05/10 08:21 AM
.*Re: DAC 2010 Report from the Floor Mikesbo   07/16/10 02:12 PM
.*DAC 2011 is San DiegoDaniel Payne  07/05/10 08:21 AM
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