>> "DIG" - Design Implementation Group for MAGMA Users
Thread views: 28937 View all threadsNext thread*

(Stranger )
05/27/03 07:12 AM
Comparator Design Report this article as Inappropriate to us !!!Login to Reply


I'm a starter in Analog IC Design, working on designing a comparator. I've currently worked out the hand calculations based on the design flow (linear reponse) given in the book "CMOS Analog Circuit Design" by Allen & Holberg. Following are the specs:

Pdiss < 5.00E-03 Watt
Tp < 2.50E-08 Sec
VDD = 5.00 V
VSS = 0.00 V
VOH > 4.50 V
VOL < 0.50 V
VICmin = 1.50 V
VICmax = 4.50 V
Vin = 1.00E-03 V
Vin(min)= 1.00E-03 V
CL = 2.00E-12 F

Gain = 72.04119782 dB
= 3999.999074 Linear

I have a few questions:

1. I'm trying to simulate my design on Cadence ADE. The time domain analysis looks to be ok. But, when I run the AC response to get the frequency/phase response of the design, the value of gain does not match with the value I have used as input for my hand calculations.

2. Am I doing the right thing by using the tool to give the frequency/phase response of the "COMPARATOR", from which I want to measure the gain. Is there a better way of doing this ?

3. I would like to know how to relate the input specifications to the design parameters/flow. It would be of great help if anyone could throw more light on this. A design example would be even more helpful.



Jump to


© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise