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01/24/06 02:29 AM
success of tape out now depends on the plan of verification Report this article as Inappropriate to us !!!Login to Reply

As Sunil (author of this article) mentioned, considering the complexity of the functionality added in today's ASIC, more than 50% of effort in a chip design goes to the functional Verification. So its obvious that verification becomes important component and clear cut plan is needed from the beginning of the project onwards to achieve the first time success. Also we need better verification plan, tools and methodology with better coverage metrics(which drives the verification) and constrain random capability(helps to automate most of the work) along with assertion based design methodology where you can use the assertions in static(formal) and dynamic simulations are needed. Reuse is another important strategy when we develop the testbench infrastucture for SoC verification to reduce the time to market. Thats the reason why we need high level verification languages(supporting OOP/AOP) like vera or e become handy for good verification. Now after the evoluation of system verilog as a unified language with testbench features and assertions may make our job more flexible if we adopt a good verification methodology and may help us to achive the first time success in shorter time.

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SubjectPosted byPosted on
*Your ASIC design better work on silicon the first time!   11/27/05 07:39 AM
.*success of tape out now depends on the plan of verificationBala  01/24/06 02:29 AM
.*As Complexities Rise, Silicon Verification is NeededPhil  12/23/05 06:03 AM
.*Complete verification is a must....Sanjay  12/07/05 03:31 PM
.*Good articleBruce_kang  12/05/05 09:35 PM
.*... and on time as well...Akiva Michelson  12/04/05 05:06 AM
.*Great ArticlePadam  11/28/05 08:42 PM
.*vinodvinod  11/28/05 03:52 PM
.*Good Articleankur arora  11/28/05 03:30 PM
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Verific: SystemVerilog & VHDL Parsers

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