At Manhattan Routing, Inc. we pride ourselves that our tools are ALWAYS validated at the next technolgy node on real chip design work by our own services group, before general release.
Since we are involved in physical design 'timing closure' tools to effectively complete the job by closing the last few hundred paths that automatic optimization tools for various reasons (tool architecture, bugs, or flawed use model) can not finish, it is critical that we are experienced in 'real' chip tape-outs. This is very different from application or consulting work, where the AE or consultant is invoved in a few steps along the way, and effectively blind to up- or down-stream issues. Instead, in these projects, we need to be knowledgable of and repsonsible for the full process of physical design, and understand when and where various trade-offs can be done that can impact everything from placement and routing efficiency to physical and functional verification.
What's at stake here is more than uncovering bugs in the tools, which of course is very important, but also the notion that the tools must be designed to do the right thing and appropriately work with all other tools within the IC design flows.