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Sandilya Bhagi
(Unregistered)
04/18/06 11:36 PM
Re: Can the chip design - verification divide be plugged in with some knee jerk band aid type strategies? Report this article as Inappropriate to us !!!Login to Reply

It was really good article which helps in understanding the process and the line "The highest quality working silicon should be 100% functional and should hit the shelves on time." is really true, and in the last the FPGA should be given more importance, all these combination will really get a good silicon in time.




Entire thread
SubjectPosted byPosted on
*Can the chip design - verification divide be plugged in with some knee jerk band aid type strategies?  04/13/06 11:35 PM
.*Functional verif is the key of successSachin  05/16/06 04:58 AM
.*Reviewed by sandeepsandeep  05/15/06 10:14 PM
.*H/w emulation gaining importanceAbhishek Goel  05/15/06 06:48 AM
.*Reviewed by Manoj KManu  05/15/06 05:10 AM
.*manish saxenamanish saxena  05/12/06 05:44 AM
.*manish saxenaMnaish Saxena  05/12/06 05:42 AM
.*Good verification strategie GivenRanveer Kumar  05/12/06 03:32 AM
.*traditional verification importancesachish  04/25/06 10:26 PM
.*Motive For VerificationSandeep Kuamr  04/20/06 11:21 PM
.*Re: Can the chip design - verification divide be plugged in with some knee jerk band aid type strategies?Sandilya Bhagi  04/18/06 11:36 PM
.*exellentsenthil  04/17/06 04:47 AM
.*Re: exellentRavikanth  04/18/06 11:27 PM
.*exellentsenthil  04/17/06 04:44 AM
.*exellentmaneesh  04/13/06 11:35 PM
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