Senior Physical Design Engineer
Experience: 5-10 years
- Responsible for physical design implementation of complex SoCs
- Participating in physical design methodologies and flow automation
- Floorplan, place, route, signal integrity avoidance/fixing, power/clock distribution, timing closure - timing, power, clock and noise analysis and DRC/LVS
- BSEE, MSEE preferred
- 4+ years of experience in block and chip level physical design in 0.13u or 90u technology.
- Must have successful track record taping out complex chips (min 2M gates) using Magma tools
- Understanding of deep sub-micron design problems and solutions (leakage power, signal integrity, antenna etc.)
- Prior experience in design timing closure, clock/power distribution and analysis, RC Extraction, place and route.
- Hands on experience in running static timing analysis (STA) tools like primetime (PT-SI). Circuit level comprehension of time critical paths in the design
- Should be a power user of P&R and analysis tools from Cadence (Frist encounter), Magma(Blast Fusion, Blast Create), Synopsys (Primetime, STAR-RCXT), Mentor (Calibre)
- Coding experience in C++, C, Perl and TCL a big plus