1. Back ground and strong interest in developing an EDA product/s:
tools based on Verilog, Vera and SystemVerilog Hardware Description Languages.
2. Very good technical expertise in formal area: SAT solvers, BDD techniques,
symbolic simulation, equivalence checkers, model checking,
constraint solver, sequential equivalence checker, etc.
3. Capable of research, but is hands on and able to break an algorithm
into projects as a technical lead.
4. Experience in managing a small team is a plus, but not a must.
Experience in doing research is a plus, but not a requirement.