Structured Design Methodology
Last Edit July 22, 2001
Compute the path propagation delay
Compute the path propagation delay for the most critical (time sensitive)
paths in the circuit. Make adjustments to the schematic in terms of macro
options for speed where needed. Does the estimated performance satisfy
the specification?
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Sum of Macro |
Sum of Macro |
Path Delay = |
Intrinsic Delays + |
Extrinsic Loading |
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Delays |
For the arrays that use typical specifications, be certain to use
the correct multiplication factor (WCM) for this worst-case analysis. Review
the assumptions made in establishing the multiplication factors and adjust
them if these assumptions are not expected to be met (i.e., derate the performance
by a higher factor). Some vendors call these multiplication factors "adjustment
factors". Be clear as to what is being adjusted and why.
There may be different multipliers for the different product grades,
Commercial and Military, and for different power supplies within the product
grade. The multiplier may depend on the macro type.
Many arrays are specified without worst-case timing multipliers. They
are specified with min/max ranges for each macro propagation delay. Maximum
path delay is found using the MAX data although the conditions for a maximum
propagation delay for an individual macro will vary. Minimum delays are
found using the MIN data.
Be certain that the proper fan-out loading and performance specifications
are selected when doing this computation. Because of the high degree of
variation in the way a library is documented between vendors and between
array series from the same vendor, be certain that the rules regarding
the methods of specifying timing delays for the macros for the array series
selected are clearly understood.
Internal extrinsic loading delays are composed of metal load (Lnet),
electrical fan-out load, the sum of all loads driven (Lfo), wire-OR electrical
loading if the array allows wire-ORs and if one was used in the net (Lwo)
and the k-factors for each. The k-factors, expressed in ns/LU, convert
the load units into time units. Table 2-7 shows the extrinsic load
equations for internal nets as they are used by AMCC and other vendors.
K-factors may be specified as tables, graphs, or broken down into parts
for temperature, voltage and processing. Check with the specific vendor.
Will the array support the maximum frequency
of operation and the critical path
performance requirements?
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Table 2-7 Components Of Path Delay - Internal Loading
General Equation for Internal Extrinsic Delay:
No wire-OR allowed:
tex = knet * Lnet+ kfo * Lfo
General Equation for Internal Extrinsic Delay:
Wire-OR allowed:
tex = knet * Lnet+ kfo * Lfo + kwo * Lwo
Worst-case Internal Extrinsic Delay:
For Arrays with a Worst-Case Multiplier:
texwc = WCM * tex
For Arrays with no Worst-Case Multiplier:
tex is already worst-case
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External extrinsic loading delays are composed of the system load capacitance
and the package pin capacitance (Lcap) and the k-factor. The k-factor,
expressed in ns/pF, convert the load capacitance into time units. The
equation used by AMCC for this delay are listed in Table 2-8.
Table 2-8 Components Of Path Delay - External Loading
General Equation for External Extrinsic Delay:
tex = kcap * Lcap
Worst-case Internal Extrinsic Delay:
For Arrays with a Worst-Case Multiplier:
texwc = WCM * tex
For Arrays with no Worst-Case Multiplier:
tex is already worst-case
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