Design Optimization
Last Edit July 22, 2001
Design To Reduce Internal Cell Utilization
Reduction of the internal cell utilization or equivalent gate count is
also called logical circuit minimization. Factoring of common terms from
the logical equation and the removal of redundant logic help reduce cell
counts by reducing the logic that must be implemented. Minimization is
critical when a high fault-grade score is desired since redundant logic
will lower the potential test score (fault masking).
Use of the higher functionality MSI macros and the design approach discussed
earlier, of selecting higher functionality macros first and working back
towards the SSI macros in the library, will contribute to a cell-efficient
design. The design approaches for internal cell minimization are shown
in Table 4-6.
Table 4-6 Minimizing Internal Cell Utilization
Reducing Internal Cell Utilization |
Logic minimization. |
High-functionality internal macros. |
Use shift counters instead of parallel counters. |
Use ripple counters if the propagation delay meets specification
delays.
|
Use ripple-carry adders (between MSI blocks). |
Use single polarity between macros. |
Use serial data transfer. |
Use a scan-test F/F or latch to replace a MUX-F/F or MUX-LATCH combination.
|
Avoid extraneous invertors (those added just to invert signals).
Many macros are available in complementary form
or use DeMorgan's theorem. |
When converting from TTL or ECL, do not implement unused functions.
Keep the macro design application-specific. |
Avoid:
- unused preset, clear
- multiple enables
- excess carry logic
- excess load logic
|
Internal cell minimization is not fully compatible with the approaches
used to improve speed. While logic minimization does help speed, as does
the use of high-functionality macros, serial operations are slower than
parallel operations. The designer must be guided by the priority assigned
to the conflicting design objectives.
Example
An experienced ECL designer chose the Q3500 array and converted a standard-part
design into macros from the chosen library. He was careful to duplicate
the parts exactly. When he was finished, he had 124% cell utilization.
At the time, there was no larger array.
The solution came when the logic was minimized and the unused functionality
of the individual standard parts was deleted from the design. By changing
the design from a direct conversion to an application-specific implementation,
the cell utilization was reduced to 98% and the circuit was built. {True
story.}
Figure 4-3 Optimization - Cell Utilization (Sizing)
Optimization Issues - Cell Utilization
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