Simulation
Last Edit July 22, 2001
Simulators - The Tools
Workstation simulators are capable of: executing partial circuits, of
tracing waveforms or lists of circuit activity, of allowing the specification
of what signals are to be traced or monitored, of allowing both internal
and external signals to be displayed, and of performing timing checks
within the accuracy of the array vendor's models. Listings and waveforms
are available in a variety of formats.
All simulations should use some form of annotation and annotation
delay files or alternative modeling procedures can be used with all simulators.
Annotation software to generate the interconnect delay files may be supplied
by the workstation or array vendor. If the array vendor does supply annotation
files or the software to generate them for the circuit, then the array
vendor's software must preempt that of the workstation vendors.
While the simulators may provide many features and output options that
the designer will find useful during the circuit development, the array
vendor may restrict the type of simulation and the output option that
may be submitted. Designers should review the chosen vendor's rules
before beginning the simulation process.
Non-Native Simulators
Several workstation graphic capture systems are no longer tied to their
native simulators or may have more than one "native" simulator.
Netlist conversion software allows selected "front-ends" to communicate
to the LASAR 6, Verilog, or other simulators that can be located on a
remote mainframe or resident on the workstation platform.
For example, as of 1994, Dazix, Valid and Mentor systems will input to
their own simulators and to the Verilog simulator. Conversion programs
allow the VAX/VMS LASAR 6 simulator to be used with the Dazix, Valid or
Mentor netlist. (AMCC made use of Lasar 6 as its RaceCheck package in
this manner.) Other combinations of front-ends and simulators are available.
The simulators that can be used will be determined by the array vendor.
Each simulator requires timing modeling for each specific library. A vendor
may support one resident simulator and not others for a given workstation.
Teradyne's LASAR 6
LASAR 6 is a software simulator originally intended as a tool to aid
Test Engineers. LASAR 6 is a true min/max simulator that correctly handles
reconvergent fan-out. Reconvergent fan-out occurs when two signals
that can be traced back to a common point must have their timing evaluated
relative to each other.
The evaluation of Tsu and Th at the input to the second stage of a shift
register would be one such case. The min/max ambiguity that exists
at the driving point of the clock net is the same at the input to both
the first stage and the second stage. It must be removed before the evaluation
of the data and clock relationship at the input to the second stage.
The need for min/max simulation is generally required because of the
possible propagation delay time differences that might occur on any two
structures on the same die. This is generally referred to as "on chip
tracking".
LASAR 6 also allows the skewing of the primary inputs to account for
the tester characteristics. This means that, if the tester specification
says that an input transition will be within plus or minus 3 ns from the
time it is told to change, then we can skew the inputs to the simulation
by plus or minus 3 ns. This makes sure that the patterns will work when
run on the tester. These advanced capabilities found in LASAR 6 are not
available in the most commonly used EWS logic simulators.
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