Last Edit July 22, 2001
Control files vary from workstation to workstation, from simulator to
simulator, from product grade to product grade, from array to array and
from simulation to simulation. They are too specific to be shown here.
The outputs of the simulators are for the most part non-compact and even
difficult to read. Only formatted outputs will be shown here. First, they
are compact, a requirement since there are 107 I/O signals and 4 internal
enable signals that the vendor requires be listed. Second, they look the
same regardless of the workstation used, Dazix, Mentor or Valid. The simula-tions
were run using Mentor.
All simulations shown are the result of military worst-case maximum timing.
Minimum simulations are often also required.
The wafer-sort and packaged-part sort test vectors are derived from the
functional simulation. (The name is vendor-specific.)
This simulation is done following vendor-specific rules. These include
high-coverage, no more than 16 outputs changing in any one vector, the
high limit allowed because parametric vectors and a parametric gate tree
All signal transitions must be included - 0-1, 1-0 for standard macros,
0-1, 1-0, 0-Z, Z-0, 1-Z, Z-1 for 3-state macros. To prevent the vector
checker from complaining, the PARAM signal from the gate tree is toggled
at the end of the vector set.
There will be one error message - the initial reset will cause 64 signals
to change state. This cannot be avoided. The circuit must be brought up
exactly as shown, with the reset "disabled", and then the reset activated.
A vector set for a 16:1 MUX is shown in Figure 8-1. Checking of this
vector set shows 100% coverage of the internal nets and primary I/O, excluding
a gate tree. It passes the vector check software with the allowed exception
of the reset error message.
Figure 8-1 Functional Simulation - 16:1 Mux
MINIMAL TEST SEQUENCE FOR 16:1 MUX
TEST CASE ON A Q20010E
1***CIRCUIT IDENTIFICATION =
1099.990 000100100111100110100101o o o o o o o o
Full File Listing - Functional, Sampled Simultation
16-Bit Register with Mux Output Sample Circuit
A partial vector set for a 32-bit register similar to that in the schematics
is shown in Figure 8-2. The sample step is 100 ns and the sample is taken
first at 99.99 ns. The simulator output is integer - place the decimal
two places from the right. The signals are listed in vendor-specified
order, all inputs, all outputs, and all 3-state enables listed last. Only
sampled func-tional simulations are submitted.
Figure 8-2 Functional Simulation - 32-Bit
8-2 Functional Simulation - 32-Bit Register - Full Listing
Create a complete functional vector set for the schematics shown in the
Appendix of Chapter 3.