Simulation
Last Edit July 22, 2001
Simulation Rules
Each vendor will have specific rules for the simulations that are to
be used to generate test vectors including: initialization, file sizes,
number of output signals that can change per vector (tester probe noise
limitation), fault coverage, procedures for three-state and bidirectional
signals, procedures for differential signals, race restrictions for data
and clock signals, and any other rules peculiar to that vendor.
A partial sample simulation output file is shown below. It is a formatted
output, sampled in 100 ns steps taken one simulator time step before the
next input vector. All inputs are uniform in their arrival and all vendor
rules were followed. This file is part of one that represents 100% fault
coverage for a simple 16:1 MUX circuit. The vectors were created following
Minimal Test Sequence rules (one input changes state per data change
vector).
Figure 8-1 Sample Simulation Output File, Formatted
To Be Used To Generate Test Vectors
TIME
9999 0100 0010 0101 1001 1010 0100
19999 1100 0010 0101 1001 1010 0100
29999 0000 0010 0101 1001 1010 0100
39999 1000 0010 0101 1001 1010 0110
99999 1001 0010 0101 1001 1010 0100
109999 0001 0010 0111 1001 1010 0100
119999 1001 0010 0111 1001 1010 0110
129999 0001 0010 0101 1001 1010 0110
o o o
o o o
939999 1000 1010 0101 1001 1010 0100
949999 0000 1010 1101 1001 1010 0100
959999 1000 1010 1101 1001 1010 0110
969999 0000 1010 0101 1001 1010 0110
979999 1000 1010 0101 1001 1010 0100
989999 0000 0010 0101 1001 1010 0100
999999 1000 0010 0101 1001 1010 0110
Full File Listing - Functional, Sampled Simultation
16-Bit Register with Mux Output Sample Circuit
At-Speed Simulation For Timing Verification
An at-speed simulation is one method that may be used to verify the actual
timing performance of the circuit as implemented on an array against the
target specification for the circuit. It is run at the maximum worst-case
conditions and at the minimum worst-case conditions. Since it is run at
the specified maximum operating frequency of the circuit, this simulation
is not used to generate test vectors.
The at-speed simulation run before layout using worst-case multipliers
and Front-Annotation can spot potential problem areas in the circuit and
to assist in defining the criteria for the layout. The Front-Annotation
file makes a statistically-based estimate of the metal delay and adds
the actual delay due to fan-out load and any wire-ORs present. Output
nets have estimated package pin capacitance and system capacitance delays.
The at-speed simulation run after layout using the Back-Annotation file
can verify the actual timing performance for the array. The Back-Annotation
file provides the actual metal delays for the layout combined with the
actual fan-out and wire-OR delays for internal nets and actual package
pin and system capacitive load delays.
Note that the at-speed simulation outputs will be time-dependent (some
results are not necessarily available within one sample step). The apparent
"phase delay" of some outputs relative to others makes the evaluation
of at-speed simulation results a non-trivial exercise.
Timing Verifier
Engineering workstations often have a timing verifier as well as a simulator.
If the array vendor supports the verifier, timing analysis using the verifier
can be substituted for At-speed simulations under the array-vendor's approval.
|