Before we compare some of the benefits of front-end in comparison to back-end in the design flow of a DSM VLSI chip, we have to reemphasize that the focus here is on the back-end. There is generally a lot of attention given to the front-end when a chip is designed.

Synthesis has always been and continues to be a fascinating field and almost the entire established EDA world is focusing on making it do all the things people want and need it to do. Only a handful of small startups are focusing on the performance issues that only the back-end can properly address. However, shrinking layout geometries are gradually bringing about a close partnership between the front-end and the back-end. It is hoped that the following discussion will help to clarify what should be a front-end to back-end synergistic relationship.

The trade-off between high levels of abstraction in the design process versus control over the details of a design is critical and needs to be carefully monitored. It is clear that, while a very high level of abstraction results in great benefits for the design process in terms of the management of complexity, its direct control over the physical aspects of a layout tends to be relatively weak. In the past, this presented few problems for the chance: of the first-time success of a VLSI chip design, because the active elements of the design determined the performance and not the layout., Because of the importance of layout parameters, these issues need to be taken increasingly seriously in design disciplines for DSM technologies, such as synthesis and floorplanning. This is emphasized by the fact that timing-driven layout is a new design discipline.

Front-end work allows a lot of freedom. Blocks can be placed and rotated, aspect ratios can be changed if needed, contacts can be moved through feed-lhroughs, metal layers can be judiciously chosen, etc. This is a lot of freedom indeed. However, it is unfortunate that while every step has far reaching consequences it is difficult to know early in the design flow what these choices will mean exactly in terms of timing by the time the physical layout is finished. Because it is so difficult to judge the parasitics resulting from a certain placement and route, the physical layout achieved at the front-end is not optimal and normally leaves a lot of room for improvement.

Anything that deals with placement of objects in a layout like postfloor-planning insertions of buffers during routing, as suggested by various authors [3,8], is nevertheless front-end work because decisions have to be made based on the best estimates. Buffers inserted into long interconnects do improve chip performance, but their dimensioning can only be done according to the best estimates and they also increase power consumption and take up real estate.

Buffer insertion was proposed quite some time ago and is still practiced. Buffer insertion to speed up long interconnects on the chip is generally done in conjunction with routing. If done later, it amounts to surgery because in a well laid-out chip it will be difficult to find empty space to place the buffers.

Since buffer insertion and their dimensioning are based on estimates, the size of these buffers often need to be adjusted once the layout is finished. Since there are optimization algorithms to dimension them for optimal performance, this is a good application for some postlayout optimization using compaction.

The literature indicates that buffer insertion was a step in the evolution of VLSI chip performance optimization. While it seems a good approach for very long interconnects, some procedures in layout optimization will be discussed that might also solve timing problems adequately without introducing more power dissipation and taking up real estate on the chip.

The major functional blocks are in place, the chip is routed. What can we still do to change performance or a chip or block at the back-end?

With the methodologies discussed here, we can only affect changes in a layout database in what we call back-end operations. Due only to “polygon pushing” can changes still be made to a chip at this point. In other words, any operations we perform on GDS2 or on any other layout database are back-end operations.

We know that the length of an interconnect is one of the parameters determining its behavior, particularly its delay characteristics. However, we can not do much about the lengths of interconnects at the back-end after routing. We also know that the width of an interconnect and its proximity to other interconnects affect its behavior and after the place and route phase, interconnect dimensions may be far from optimal. Fortunately, we can still adjust the widths of interconnects and their proximity to other interconnects quite a bit in the postlayout phase by using compaction and other algorithms working at the polygon level.

The same may be true for the reuse of an existing chip with Hard IP migration from process to process. So there is still quite a lot that can be adjusted on a “finished” layout.

We need to look at the proper dimensioning of interconnects and a balancing of lengths or, more accurately, a balancing of time delays on some of them. We should just briefly mention here that balancing lengths of interconnects will generally not assure equal time delay in these interconnects [3]. We simply need to take a very good look at many of the characteristics of interconnects in the interest of maximizing chip performance.

Clearly the degree of freedom for major changes is largest at the front-end during synthesis, floorplanning and routing. Because of this, we may have to restart with these early steps if we need to fix a chip that totally missed its target. Unfortunately, a lot of rework has to be done with such changes and the desired timing may in the worst cases be approached only with several retries. Maybe, we can fix a timing problem by just inserting a buffer here and there in long interconnects and, if that alone does not quite fix the problem, the strength of the buffer stage can be adjusted with compaction. Actually, as we discuss in the next section, we may even insert a buffer stage in the postlayout phase.

Finally, while the degrees of freedom for postlayout corrections are more limited, an advantage is that the results caused by changes are very predictable. In the case of less dramatic deviations from timing, we may just use some of the optimization steps that are discussed in this chapter.

Within the available real estate on a chip any polygon edge can be shifted around as long as its position satisfies all the process rules. Also, as pointed out before, none of the polygon edges can “jump over” any of their neighboring polygon edges. This flexibility in placing polygon edges can be very useful. It is in sharp contrast to a linear shrink and provides the following benefits:

Compaction can actually free up space for additional components!

When performing a linear shrink, all polygon edges move together according to some proportionality factor. When compaction is applied, all polygon edges move to a place prescribed by process rules or user input. We could for instance insert a miniature buffer stage into a long interconnect that exhibits timing problems in the postlayout phase. This insertion would most probably be done manually with a layout editor. Compaction could then enlarge this buffer stage to the desired size by pushing other polygon edges aside while enforcing all the process layout rules. In Figure 3.1, we show how a miniature feature can be inserted in the left layout. Compaction then enlarges it to do what it is supposed to do while satisfying all the layout design rules, as shown in the right layout. While the inserted feature in Figure 3.1 is not a buffer, any shape that potentially fits is possible, like a buffer for a long interconnect.

Fig. 3.1 Compaction Can Make Space for Inserted Features

As we will see when discussing spreading out interconnects in Figure 3.9, space is often available. Of course, it is a trade-off. Some space has to be sacrificed for the benefit of the whole, which means that the procedure is limited. However, pushing neighboring polygons aside for the benefit of others is not possible with linear shrink. Needed space is actually created, although it is a matter of give and take.

Of course, back-end optimization can not save a badly designed chip! With all the leverage possible with back-end optimization, the degree of leverage after layout may not be enough to eliminate timing problems in a very bad floorplan. It is better to redesign from scratch to obtain a better starting point for the layout optimization to follow. But with a “reasonable” floorplan and “reasonable” route, back-end adjustments in a layout can profoundly affect and improve chip timing performance.

At the back-end, we start either with a chip that needs to be retargeted to a more advanced process or a chip that has been newly designed up through place and route.

We already know a lot about a chip's behavior in order to be able to retarget it. The chip has a track record. We know that it is functionally correct. We can also compare the way the chip actually worked to the chip analysis conducted before fabrication. This information of actual performance data, which is generally difficult to predict accurately, is very valuable, especially for the timing, But now that the chip is fabricated in a new process, the timing will undoubtedly shift and the layout has to be adjusted. Fortunately, constant advancement in tools currently provides us with optimization algorithms for the physical layout that did not even exist during the initial design of the chip. This means we may now have a much improved means to get a better chip.

Of course, what we can not change is the “topology” of the layout, how the blocks are functionally connected together.

This is good because we do not want to redesign - we want to reuse!

For a chip that has just been designed and laid out, the architecture is fixed, the floorplan is fixed, the routing and all the transistors are in place and, based on estimated parasitics for the process to be used, its timing works. So the focus for such a chip is not to just make it work but to make it work even better, to optimize its performance. To achieve this, we can adjust the geometrical dimensions and shapes of transistors, the widths and the separation of interconnects. We can change the sizes and shapes of capacitors and resistors.

Another important aspect of layout that receives increased attention lately is the fact that VLSI circuits often have the minimally allowed layout dimensions in many places where this does not result in any increased performance. This often just lowers the yield and negatively affects the reliability that can be achieved for the fabrication process. In fact, it may lower the performance of a chip, as will be discussed later. It is critical that layout dimensions be optimized for maximum density, but without sacrificing yield or performance. This type of optimization is easily done with compaction and is very powerful.

Finally, reasons for late layout adjustments may be based on more than just optimizing the performance of a chip. There may be some serious timing problems in the chip that are due to changes in some process parameters, perhaps to changes in metal resistance, perhaps to changes in the permittivity of the oxide (the k value), to mention just a few possibilities. Many things could be responsible for a chip not working. There is no point in guessing in advance what they might be. The point is, if adjustments in layout dimensions can solve the problems, the presently discussed methodology provides the means to fix them.