MIPS selects Imperas Reference Models for RISC-V Processor Verification

The RISC-V Summit and DAC are co-located for 2021, running December 6-8 in San Francisco, CA.
Imperas is a Diamond Sponsor for the RISC-V Summit 2021; more details on all the keynotes, talks and to request a demo are available at this link.

About MIPS
MIPS is a leading provider of RISC-based processor architectures and IP cores that drive some of the world’s most popular products. With the streamlined MIPS RISC-based architecture and CPU cores, semiconductor designers can create efficient, scalable and trusted products across a wide range of performance points – from the IoT Edge to high-end networking equipment, and everything in between. Further details are available at www.mips.com.

About Imperas
Imperas is the leading provider of RISC-V processor models, hardware design verification solutions, and virtual prototypes for software simulation. Imperas, along with Open Virtual Platforms (OVP), promotes open-source model availability for a spectrum of processors, IP vendors, CPU architectures, system IP, and reference platform models of processors and systems ranging from simple single core bare metal platforms to full heterogeneous multicore systems booting SMP Linux. All models are available from Imperas at www.imperas.com and the Open Virtual Platforms (OVP) website.

For more information about Imperas, please see www.imperas.com. Follow Imperas on LinkedIn, twitter @ImperasSoftware and YouTube.

All trademarks or registered trademarks are the property of Imperas Software Limited or their respective holders.

Issued by:
Dulcie Elliot, Publitek
Tel: +44 7912 307 170 E-mail: dulcie.elliot@publitek.com



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