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Video's Title
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Company
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Views |
| Using the Xilinx Power Estimator | Xilinx |
1507 |
| Using the Pin Editor in Cadence SoC-Encounter | Cadence |
4859 |
| Using IP/SoC Executable Specifications and Integration with Formal Verification | Jasper |
1561 |
| Using Global Timing Debug on a Single Path in Cadence SoC-Encounter | Cadence |
3890 |
| Using --Apply All-- in Cadence SoC-Encounter | Cadence |
1922 |
| Tom Anderson discusses how apps are changing EDA | Breker Verification |
1026 |
| SoC Integration | Jasper Design Automation |
771 |
| Sam Appleton, CEO | Ausdia |
1657 |
| Rupert Baines, CEO | UltraSoC |
1022 |
| Running Cadence SoC-Encounter...on an iPhone | Cadence |
3924 |
| Rob van Blommestein, VP of Marketing | S2C |
1561 |
| Riviera-PRO™ Overview: Advanced Verification Platform | Aldec |
1305 |
| RAAAM: The Highest Density Memory in Standard CMOS | RAAAM Memory Technologies |
2885 |
| Pre-silicon D&V innovation and standardization efforts from Accellera | Accellera |
4533 |
| PolarFire SoC FPGA Brings Real-Time to Linux | Microchip |
2302 |
| Piyush Sancheti, V.P. Marketing | Atrenta |
655 |
| Partitioning a Design in Cadence SoC-Encounter | Cadence |
5855 |
| NVIDIA Press Event at CES 2018 with NVIDIA CEO Jensen Huang | Nvidia |
1891 |
| Low Cost Top View IP with only 2 cameras (Front and Rear) for Cyclone V SoC | Altera |
316 |
| Keynote speech by Jim Hogan: Making Money from SoC Realization – where are we today? Part 2 | Atrenta |
2948 |
| Keynote speech by Jim Hogan: Making Money from SoC Realization – where are we today? Part 1 | Atrenta |
2984 |
| Keynote By Dr. Ajoy Bose : SoC Realization – Building a Bridge to New Markets and Renewed Growth Part 2 | Atrenta |
3129 |
| Keynote By Dr. Ajoy Bose : SoC Realization – Building a Bridge to New Markets and Renewed Growth Part 1 | Atrenta |
2903 |
| Jeff Scott, Principal ARM SoC Architect | Open-Silicon, Inc. |
877 |
| Jean-Luc Triouleyre, CEO | IC’Alps |
1748 |
| Introduction to the ARM CoreLink CCI-500 | ARM |
592 |
| Introduction to ARM Socrates IP Tooling | ARM |
949 |
| Interview with Toshio Nakama, CEO | S2C |
1581 |
| Interactive Floorplanning in Cadence SoC-Encounter | Cadence |
4471 |
| How to create innovative architecture using VisualSim? | Mirabilis Design Inc |
764 |
| HES™ Overview - A Hybrid Verification and Validation Platform | Aldec |
1022 |
| Graham Curren, CEO | Sondrel |
3108 |
| FPGA-adaptive debug on the Altera SoC using ARM DS-5 | ARM |
391 |
| Detecting System-Level Corner Cases During Low-Power SoC Verification | Cadence |
461 |
| Designing a Multimedia SoC using system-level simulation | Mirabilis Design Inc |
1024 |
| Debugging Linux applications on the Altera SoC with ARM DS-5 | ARM |
547 |
| AMD at Computex 2021 | AMD |
3969 |
"SOC Integration, IP Promotion, and fixing Release Paralysis",
Simon Butler | Methodics |
1712 |
"New SOC FPGA Debug",
Dave Orecchio | GateRocket |
1739 |
| "LOVE! and SOC Realization is a Bridge From System to Silicon", Happy Honeymooners and Jim | Atrenta |
2867 |
